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Home / AFL Blog / May 2017 / The Path to 100G Single Lambda in the Data Center - Part 2
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The Path to 100G Single Lambda in the Data Center - Part 2

Maury Wood, AFL Test & Inspection Product Line Manager

Part 2 (Part 1 - Part 3)

Welcome to part two of this blog series on the technical and commercial dynamics that will lead the semiconductor and electro-optical components industries to 100G single lambda system over the next several years.

Obviously, modern networking infrastructure equipment has broad scope.  For the purposes of this analysis journey, we'll constrain ourselves to the physical layer technology that begins and ends with a layer 2/3 Ethernet switch.

While not definitional, in end-to-end 25G single lambda signal chains, the electrical SerDes rate in the chip-to-module interface between the switch ASIC and the pluggable transceiver also runs at 25 Gbps (or 28 Gbps to account for 64B/66B encoding and FEC overhead when used).

So the first challenge to 25G single lambda is a 28 Gbps electrical SerDes.  This is by no means a trivial accomplishment.  FPGA suppliers Altera/Intel and Xilinx were first able to offer this operating frequency in their 28 nm Stratix V and Virtex 7 product platforms in 2011.  Switch ASIC leader Broadcom was able to offer this operating frequency in their 28 nm Tomahawk ASIC (with 7B transistors) in September 2014.  Based on FPGA roadmaps and switch ASIC roadmaps, it is likely that 30-33 Gbps NRZ (56 Gbps PAM-4) SerDes will become available in the 16/14 nm FinFET+ generation which sees production this year (2017).  The assumption here is "NRZ" signaling (1 bit per symbol) will be used in the 56 Gbps generation, then move to 56 GBaud PAM-4 for the 112G single lambda generation.  Aquantia, Credo Semiconductor, Broadcom and others have made technology and product announcements on 56 Gbps discrete PHY solutions recently.  We'll come back to this topic, but drop a pin in this part of the signal chain, because it is instructive to point out that the OIF CEI-56G-VSR and CEI-112G-VSR CAUI chip-to-module interfaces only reach through 10 cm of copper, and use heavy doses of TX pre-emphasis, RX equalization and even Reed Solomon Forward Error Correction.  This illustrates the relative ease with which photons travel through pure silica glass compared to the tough slog faced by electrons in copper, even with exotic PCB materials.


25g-eye-diagram.png
25G Eye Diagram


Okay, we'll start next time with a quick discussion about information theory – it’ll be fun!


Posted: 5/12/2017 by | with 0 comment(s)
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