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Home / AFL Blog / May 2018 / The Path to 100G Single Lambda in the Data Center - Part 6
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The Path to 100G Single Lambda in the Data Center - Part 6

Maury Wood, Test & Inspection

There have been a significant number of key photonic component and technology announcements since the last installment of this blog series. These announcements are clear evidence of the growing industry ecosystem support for 100Gbps single lambda (100GSL), enabling 200G and 400G Ethernet links in enterprise and hyperscale data center optical networks. Most critically, 100GSL allows duplex 400G (IEEE 802.3bs) using parallel optics on a single MPO-12 multifiber cable assembly (for example, the 500 meter reach 400GBASE-DR4 / PSM4 and the 2 km reach 400GBASE-FR4). At least three 400G ready Multi-Source Agreement (MSA) pluggable module definitions will leverage 100GSL technology: QSFP56-DD, OSFP and CFP8. The COBO (Consortium for On-Board Optics) MSA is also likely to adopt 100GSL for their proposed 400G and 800G frontplane, midplane and backplane solutions. Additionally, the 100G Lambda MSA Group was established in September 2017, and released their first specifications in January of this year. Things are certainly moving fast!

These recent announcements can be organized into three categories: electrical interface standards and switch ASICs; PAM4 DSPs; and PAM4 electro-optic (EO) modulation components.

Electrical Interface Standards and Switch ASICs

On January 16, 2018, the Optical Internetworking Forum (OIF) announced the publication of the Common Electrical I/O CEI 4.0, which pertains to 56 Gbps NRZ, Ensemble NRZ and PAM4 SerDes (Serializer/Deserializer) interfaces such as those between switch ASIC chips and pluggable optical modules. This industry standard includes ultra-short reach, extra short reach, very short reach, medium reach and long reach electrical specifications to span die-to-die to connector-over-backplane applications. The OIF CEI 4.0 specs will be used in four lane CDAUI-4 / GAUI-4 for 200G and eight lane CDAUI-8 / GAUI-8 for 400G systems (such as those using OSFP and QSFP-DD transceiver modules).

Broadcom, long the dominant supplier of merchant (open market) Ethernet switch chips, announced the 16nm Tomahawk3 switch ASIC in December 2017 with 256 count PAM4 SerDes channels at 56G, yielding 128 100GbE (or 32 ports of 400G Ethernet) for an aggregate bandwidth of 1.2 Tbps per 16nm process technology chip. Xilinx offers 56G PAM4 SerDes in their 16nm FinFET+ Virtex UltraScale+ FPGAs, announced in May of 2017, and Altera/Intel announced 56 Gbps PAM4 SerDes for their Stratix 10 FPGAs in the same month in 2016. FPGAs are used by some Ethernet switch makers, who prize their rapid reconfigurability.

There is wide industry analyst speculation that the next generation of 10nm switch ASICs and FPGA chips will offer direct optical I/O, most likely using interposer packaging technology and possibly silicon photonics (SiPh).

PAM4 Digital Signal Processors

According to the publication Semiconductor Engineering, the average design cost of a 16nm biCMOS or FD-SOI FinFET chip is roughly $80M from start to finish. With this in mind, it is quite remarkable to see the financial commitment being made by several companies in the domain of PAM4 100GSL / coherent DSP chips at the 16nm semiconductor process technology node.

Here is a sampling of the feverish activity in this area:

  • MultiPhy announced the FlexPhy MPF3101-SRW in February. This DSP includes extremely high speed mixed-signal ADC and DAC functions, as well as support for advanced FEC schemes such as MLC-BCH and staircase coding.
  • In March, Infinera announced the ICE5 – Infinite Capacity Engine – comprising both a photonic IC and their FlexCoherent DSP with capacity to a remarkable 600G per lambda.
  • In March, NeoPhotonics announced its ClearLight CFP Digital Coherent Optics (DCO) transceiver based on a 16nm CMOS DSP.
  • Inphi announced the Vega 16nm PAM4 Retimer and Gearbox family, with embedded InphiNity™ DSP engine in August 2017. The Inphi M200 LightSpeed-III 16nm coherent DSP was announced in September 2017; this device includes a FIPS compliant AES256 encryption engine.
  • Ciena announced their latest WaveLogic3 Ai coherent DSP in March of this year. It includes Tx and Rx engines as well as a soft FEC embedded engine.
  • MACOM announced the 16nm FinFET MATP-40050 PRISM4 in March in conjunction with ColorChip. This device includes a network interface with four bidirectional lanes of 53 GBaud PAM4 (106 Gbps), integrated linear laser drivers, as well as a DSP-based FEC and equalizer to support SMF links reaching 2 km.
  • In March, Nokia announced the PSE-3 Photonic Service Engine coherent DSP, which utilizes an advance in spectral efficiency called probabilistic constellation shaping and that in combination with 64-QAM modulation, can also support 600G per lambda.
  • NTT Electronics announced their ExaSPEED 200 16nm FinFET 64 GBaud coherent DSP for DWDM application in March. This device also supports up to 600G per lambda using 64-QAM, and was developed in collaboration with Broadcom.
  • In January, MaxLinear announced the 16nm Telluride MxL935XX DSP SoC family with integrated electro-absorption externally modulated laser (EA-EML) driver for 400G interconnects, with a claimed power dissipation of 6.7W to meet QSFP-DD, OSFP and COBO requirements. Variants of this family are also suitable for use with silicon photonics. All members include transmit digital pre-distortion (DPD) and comprehensive receive equalization (CTLE, AGC, FFE and DFE).

PAM4 EO Modulation Components

There has been a corresponding flood of announcement in PAM4 electro-optic modulation components that support 100GSL.

  • In September of last year, MACOM announced the MATA-03819/03919 quad 53 GBaud TIA family, the PT-28E differential-output reference receiver module, and MATA-03820 four channel 100G linear TIAs for 53G Baud PAM4. MACOM also announced the MAOP-L561PP photonic integrated circuit with a high bandwidth (56G) Mach-Zehnder modulator including a four lambda CWDM multiplexer, plus a 1310 nm CW DFB laser. An integrated tap detector is provided for fiber alignment and closed loop control.
  • In March, Oclaro announced 64G Baud micro-intradyne coherent receiver (micro-ICR), integrated coherent transmitter (ICT), high bandwidth co-package driver modulator (HB-CDM), and high bandwidth lithium niobate polarization-multiplexed quadrature Mach-Zehnder (PM-QMZ) modulator, and 100 kHz micro-integrated tunable laser assembly (micro-ITLA), compliant to OIF CEI standards. While these components are intended for coherent transceiver solutions more typical of long haul applications, they underscore the technology evolution underway for 400G transmission. Also in March, Oclaro announced availability of its 100G PAM4 EA-DFB EMLs.
  • NeoPhotonics announced a family of 53GBaud linear optical components in March. This family includes an open drain driver (ODD) for Externally-Modulated Lasers (EMLs), a quad Mach-Zehnder module (MZM) driver, a CWDM4 EML, PIN photodetectors, and a Transimpedance Amplifier (TIA).
  • MaxLinear in March announced the MxL9154 PAM4 400G quad channel linear TIA, which achieve 3% linearity up to overload conditions, and a bandwidth of more than 25 GHz, making them ideal for 100GSL transceiver applications. MaxLinear claims the die size of this device enable it to meet the quad-ROSA size restrictions of both QSFP-DD and OSFP module form factors.

These impressive 100GSL technology and component announcements signify the development of a very healthy industry ecosystem that will deliver a variety of 400G short reach transceiver modules in 2019. It is remarkable to consider that 2017 was hailed as the year of 100G deployment in hyperscale data centers, and that just three to four years later, production quantity of products offering a quadruple speed upgrade will be available to support the voracious and insatiable worldwide demand for broadband information access.

Posted: 5/10/2018 by AFL | with 0 comment(s)
Filed under: Data Center, Test and Inspection
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